adding some microsecond delay in vhdl program..

[gauree]

i m writing a vhdl program and i want to add in that program 125 microsecond delay but how to do it i don't know if any one know help me..

 

[sureshaa]

Hi gauree,

Please clarify, whether you are trying to write a test bench or Design?
If it is test bench you can use wait statement. If it is Design program using source clock try to add flops.Hope it will helpful to you.

 

[gauree]

thank you , your reply is helpful