Adding initial value for VCO in PLL

[mino]

When I simulated PLL in hspice , I need to add initial value for VCO and VCO will be oscillated.
But, Do I need to add the other circuit for VCO in order to give it initial value on layout ?

 

[Analog_starter]

Re: Question about PLL

No, you do not need.

Best Regards,
Analog_starter

 

[yibinhsieh]

Re: Question about PLL

In hspice, when we add an initial value in VCO, that will help HSPICE to oscillate the VCO. That's hspice algorithm. In real circuit, it will be oscillated if your VCO is correct because it always have noise in VCO. So you don't add any circuit in your VCO.


Yibin.

 

[huanchou]

Re: Question about PLL

Maybe you can try to add some conditions into the run file.
For example, add the power ramp (from 0 to vdd) or add the interference in the
power rail to model the real environment.
If your circuit can't osc with above conditions, maybe it have some unknow side effect.

 

[mino]

Re: Question about PLL

Thank everybody's answer .
I will check my circuit on layout.

Added after 26 minutes:

and, I have a question in testing.
Where is the boundary line that frequency limits between on bread board and on PCB ?

 

[yibinhsieh]

Re: Question about PLL

and, I have a question in testing.
Where is the boundary line that frequency limits between on bread board and on PCB ?

If you want a full digital swing output and get a good jitter peformance. Maybe below 150MHz is a suggestion.

Yibin.

 

[vbhupendra]

Re: Question about PLL

we use a pwl source for vdd to simulate PLL instead of giving initial condition. though initial condition reduces simulation time.

 

[layes2]

Re: Question about PLL

of course you need not to do that

 

[tuncili]

Question about PLL

hello i am looking for pll examples and designs using simulink. specially synchronization with pll.

anyone have anything ..

very thanks

 

[Yun Lin]

Question about PLL

If you want to test high frequency PLL, such as more than 200Mhz, you must care the high speed IO design.