Adding full custom layout to GDS.

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I want to add an ADC to the RTL to GDS flow of my SoC. I have the layout (GDS) of the ADC. How to do this?

I have access to Cadence ans synopsys toolchain. I have done the RTL to GDSII flow for the Processing system part.

But since ADC is non synthesizable(Full custom). I have no clue how to add that to the flow.
 

ADC becomes a macro element like a pad or a standard cell.
the question is who should merge both, in which tools?

If the final gds is generated by innovus, you need to have a RTL code which instantiate this ADC + the processing system.
The ADC instance must have a liberty, LEF files to be know by the synthesis and PnR tool (as well for all others physical tools, like LEC, STA, ...).
 

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