well, normaly the std cell library provided some filler cell to fill the n-well and power rail between two std cell.
but this step should be done by the PnR tool, not in virtuoso, or do you made a small block in the analog tool env?
The filler cells are here to respect the DRC between two std cell not abuded.
Yes I made a small block in virtuoso containing <20 transistors and is importing this block as macro in PnR tool (Encounter)
My question is that whether I have to add fillers to the block designed in virtuoso (I have connected all CMOS nwell,pwell to vdd,gnd manually in virtuoso)? If yes whether that should be done in virtuoso itself ? or is there provision to do it in encounter (adding filler to a macro from top level!! ) ?
How can I add filler in encounter when the block is a hardmacro ?good if you can share command pleas..
I agree we can add to top level in encounter . . my question is specific to block designed in virtuoso and loaded as macro(block) to encounter