E
expertengr
Guest
I just read Chapter 21 of the data sheet of PIC18F2550 but I have some questions. From the Table 21-1 it look like that TAD (A/D conversion time per bit) depends on the A/D conversion clock which can be set by ADCS2:ADCS0.
https://ww1.microchip.com/downloads/en/DeviceDoc/39632e.pdf
Let's suppose FOSC is constant, consider the following two settings
1- Writing 000 to ADCS2:ADCS0 make A/D conversion clock FOSC/2 and according to Table 21-1 TAD is 2 TOSC.
2- Writing 100 to ADCS2:ADCS0 make A/D conversion clock FOSC/4 and according to Table 21-1 TAD is 4 TOSC.
The sampling rate in Setting 2 is two times slower then setting 1 because the bit conversion time TAD in Setting 2 is 4 TOSC which is two times slower than bit conversion time TAD in Setting 1 as TAD is 2 TOSC. This is understandable. This means if we change FOSC it can also change TAD. Is there any minimum value for TAD ?
As the minimum acquisition time is 2.45 u sec according to Equation 21-3. The design parameter here is acquisition time which can be set by ACQT2:ACQT0 in terms of TAD and it should be more then 2.45 u sec. Is that correct ? For faster conversion we should have TAD as low as possible but greater then which value, any minimum value of TAD for stability ? and acquisition time little above 2.45 u sec. Please let me know if this is correct ?
In Table 21-1 what Maximum Device Frequency represents ? As writing 110 to ADCS2:ADCS0 configure 64 TOSC which represents slower A/D bit clock TAD and more acquisition time but why the Maximum Device Frequency is higher i.e. 48 MHz ?
https://ww1.microchip.com/downloads/en/DeviceDoc/39632e.pdf
Let's suppose FOSC is constant, consider the following two settings
1- Writing 000 to ADCS2:ADCS0 make A/D conversion clock FOSC/2 and according to Table 21-1 TAD is 2 TOSC.
2- Writing 100 to ADCS2:ADCS0 make A/D conversion clock FOSC/4 and according to Table 21-1 TAD is 4 TOSC.
The sampling rate in Setting 2 is two times slower then setting 1 because the bit conversion time TAD in Setting 2 is 4 TOSC which is two times slower than bit conversion time TAD in Setting 1 as TAD is 2 TOSC. This is understandable. This means if we change FOSC it can also change TAD. Is there any minimum value for TAD ?
As the minimum acquisition time is 2.45 u sec according to Equation 21-3. The design parameter here is acquisition time which can be set by ACQT2:ACQT0 in terms of TAD and it should be more then 2.45 u sec. Is that correct ? For faster conversion we should have TAD as low as possible but greater then which value, any minimum value of TAD for stability ? and acquisition time little above 2.45 u sec. Please let me know if this is correct ?
In Table 21-1 what Maximum Device Frequency represents ? As writing 110 to ADCS2:ADCS0 configure 64 TOSC which represents slower A/D bit clock TAD and more acquisition time but why the Maximum Device Frequency is higher i.e. 48 MHz ?
