No I am not having serial interface, its a 16 bit parallel interface .
following is the link for data sheet ADC 7656
HTML:
http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad7656/products/product.html
currently in one condition adc_busy is coming , but I still need your help -
I am able to reset the device when I am sending convert_start and checking for 5 us and
if adc_busy is not coming then I am resetting the device hoping that the adc should recover
and start sending adc_busy again. and I am successful in doing so.
But I need to keep on resetting the ADC until adc_busy comes, When I try to do that,
ADC_BUSY stops coming from ADC. ADC_BUSY is an input port to FPGA, so FPGA cannot drive ADC_BUSY pin.
I am posting both the codes, one which is working and one which is not working. P
lease suggest me where am I wrong in the implementation.
Also even if I try to modify 1 line from the current working code, the ADC_BUSY stops coming.
---- this code is working but is capable of resetting only until all adc_busy goes high.
---- required implementation is to keep on resetting every 5 us until all adc_busy goes high.
p_Rst_frm_RCI_reg: process(int_clk_100mhz) is
begin
if(falling_edge(int_clk_100mhz))then
if (adc_reset_busy_error = '1' and adc_reset_busy_error_dly = '0') then
adc_reset_busy_error_sig <= '1' ;
elsif adc_reset_busy_error_clr = '1' then
adc_reset_busy_error_sig <= '0' ;
end if;
end if;
end process p_Rst_frm_RCI_reg;
--- state machine starts -----
case adc_state is
when idle_state =>
if(rci_start_acq_fl = '1' or adc_reset_busy_error_sig = '1') then
if(adc_rst_bsy_cnt = ADC_RESET_DURATION)then
adc_convst_sig <= (others => '0');
adc_rst_bsy_cnt <= (others => '0');
adc_reset <= '0';
adc_state <= convst_state;
adc_reset_busy_error_clr <= '1' ;
else
adc_convst_sig <= (others => '1'); -- Must be high during reset
adc_rst_bsy_cnt <= adc_rst_bsy_cnt + '1';
adc_reset <= '1';
adc_state <= idle_state;
end if;
else
adc_convst_sig <=(others => '0');
adc_state <= idle_state;
end if;
when convst_state =>
adc_reset_busy_error_clr <= '0' ;
if(frac_sec_count = 0) then -- checking for pps edge
adc_state <= adc_busy_state;
else
adc_convst_sig <= (others => '0');
adc_state <= convst_state;
end if;
when adc_busy_state =>
adc_convst_sig <= adc_convst_out; ---- sending convert_start signal to ADC
if (adc_const_int1 = '1' and adc_const_int2 = '1' ) then
if(adc_rst_bsy_cnt < BUSY_STATE_DURATION) then -- waits for 5 us
adc_rst_bsy_cnt <= adc_rst_bsy_cnt + '1';
adc_state <= adc_busy_state;
elsif (adc_busy_high = '1' ) then
adc_reset_busy_error <= '0';
adc_state <= adc_cs_state;
adc_rst_bsy_cnt <= (others => '0');
else
-- if adc_busy doesn't go high even after 5us after conver_start
-- then adc_reset_busy_error goes high.
-- but fpga will still go to next state and after completion of 1 complete
-- data cycle it will go to idle state where it will reset the ADC
adc_reset_busy_error <= '1';
adc_state <= adc_cs_state;
adc_rst_bsy_cnt <= (others => '0');
end if;
else
convst_en1 <= '1' ; -- Enable to generate convert start
convst_en2 <= '1' ;
end if;
----- continue with other states ----------
------------------ Modified code , the following code doesn't work ---------------------
p_Rst_frm_RCI_reg: process(int_clk_100mhz) is
begin
if(falling_edge(int_clk_100mhz))then
if (adc_reset_busy_error_dly = '1') then ---- checking for level
adc_reset_busy_error_sig <= '1' ; ---- rather than checking for edge.
else
adc_reset_busy_error_sig <= '0' ;
end if;
end if;
end process p_Rst_frm_RCI_reg;
--- state machine starts -----
--- state machine starts -----
case adc_state is
when idle_state =>
if(rci_start_acq_fl = '1' or adc_reset_busy_error_sig = '1') then
if(adc_rst_bsy_cnt = ADC_RESET_DURATION)then
adc_convst_sig <= (others => '0');
adc_rst_bsy_cnt <= (others => '0');
adc_reset <= '0';
adc_state <= convst_state;
else
adc_convst_sig <= (others => '1'); -- Must be high during reset
adc_rst_bsy_cnt <= adc_rst_bsy_cnt + '1';
adc_reset <= '1';
adc_state <= idle_state;
end if;
else
adc_convst_sig <=(others => '0');
adc_state <= idle_state;
end if;
when convst_state =>
if(frac_sec_count = 0) then -- checking for pps edge
adc_state <= adc_busy_state;
else
adc_convst_sig <= (others => '0');
adc_state <= convst_state;
end if;
when adc_busy_state =>
adc_convst_sig <= adc_convst_out; ---- sending convert_start signal to ADC
if (adc_const_int1 = '1' and adc_const_int2 = '1' ) then
if(adc_rst_bsy_cnt < BUSY_STATE_DURATION) then -- waits for 5 us
adc_rst_bsy_cnt <= adc_rst_bsy_cnt + '1';
adc_state <= adc_busy_state;
elsif (adc_busy_high = '1' ) then
adc_reset_busy_error <= '0';
adc_state <= adc_cs_state;
adc_rst_bsy_cnt <= (others => '0');
else
-- if adc_busy doesn't go high even after 5us after conver_start
-- then adc_reset_busy_error goes high.
-- but fpga will still go to next state and after completion of 1 complete
-- data cycle it will go to idle state where it will reset the ADC
adc_reset_busy_error <= '1';
adc_state <= adc_cs_state;
adc_rst_bsy_cnt <= (others => '0');
end if;
else
convst_en1 <= '1' ; -- Enable to generate convert start
convst_en2 <= '1' ;
end if;
----- continue with other states ----------