ADC for CMOS Image Sensor

[hacksgen]

image sensor adc

Hi guys,

I would like to know what all I have to consider while designing an adc for CMOS Image sensor. The image sensor is to be used in industrial applications or cinematic high definition applications. The image sensor will have an array of 4000x3000 pixels size and have a framerate of about 200 frames/sec. So a column parallel adc implementation will be done. The architecture I am looking at currently for implementaiton is a SAR ADC with 12 bit resolution.
How should the dynamic range, linearity be taken into consideration. Can anyone explain to me the effect of adc characteristics such as differential non linearity (DNL) or integral non linearity(INL) of more than ±1 on the image data obtained from the image sensor. Or perhaps a book which explains all these.

Thanks,

 

[dineshbabumm]

cmos image sensor noise characterization

Having INL of more than +/- 1 LSB means you will have missing codes.. For instance say there are 8 bit which means 256 codes.. There will be some missing codes in this.. Say code 120 and 56 is missing.. So that means there will be wrong code at the output and this might affect that particular pixel! So it is better not to have more than 1 LSB in INL.. Try to keep it as low as possible.. INL and DNL means the static error in system level and not dynamic(That is this error is not due to change in the signal)..

CMOS Data converters for Communications by Gustavsson is the book I followed while I did my project.. it is a very good book and I suggest you can also follow that to understand these concepts like INL, DNL and other dynamic errors....

 

[PaloAlto]

eda board adc cmos image sensor

Having INL of more than +/- 1 LSB means you will have missing codes.

I am afraid that is not true. You can have INL that smoothly changes from -10 to +10LSB and have no missing codes, but:

Having DNL of more than +/- 1 LSB means you will have missing codes. :wink: :wink: :wink: :wink: :wink: :wink:

In fact, if I remember it correctly DNL should be less than +0.9LSB to have guaranteed monotonicity.

 

[leili]

cmos image sensor sar adc

There are many things to consider when designing ADC for CMOS image sensors. E.g.

1. With the column parallel architecture you will not have one converter you will have 4000 (or 8000 if placed at top and bottom). Each ADC will have its own transfer curve and, thereby, its own INL and DNL curves. Variations in transfer curves between the ADCs can be characterized as fixed pattern noise (FPN).

2. A cmos image sensor has low noise for weak signals but high noise for high signals (due to photon shot noise and pixel FPN). With a 12b conversion pixel FPN and temporal noise can be around maybe 30 LSB or so for high signals.

3. The pixels are not very linear due to the charge to voltage conversion and the source follower. The INLmax from the pixel may be around 1% of the swing, which means around 40 LSB with a 12b converter.

2 and 3 should be used when designing the ADC.

4000x3000 pixels at 200fps and 12b ADC seems challenging! SAR is fast but you might get problems with 12b. Have you considered a simultaneous multislope converter with fast pseudo conversion (**broken link removed**). Please read section 3 in the paper, it is about ADC characterization for image sensors.

I haven't read the book CMOS Data converters for Communications, but I have had Gustavsson as a teacher and I have worked with the co-author Jacob Wikner. I guess the book ought to be good.

 

[hacksgen]

cmos sensor sar adc

I do know 12bits for sar is a problem without calibration. but the fact is i have to use this converter nonetheless. thanks for the paper. right now i am doing some simulations using behaviourtal models.
i noticed that i am getting wide codes for the transitions at bit 8,8,10,11,12. that is the minimum analog voltage difference required for the change to occur in that particular bit is large because of which my DNL is going above 1LSB. although the monotonicity is still maintained and there are no missing codes however i would still like to reduce the dnl to a value less than 0.5 LSB.

can anyone explain the cause and perhaps a solution for the wide codes. i am using sar with capacitor array for charge redistribution. i am also using some non ideal modeling like on and off resistances for the switches and rise and fall times for the signals.

thanks

 

[leili]

cmos sensor adc

Maybe you have already solved this, but I would have checked charge injection and clock feedthrough from the switches. With 4000 columns I guess you have a pitch of about 4um. With 2000 ADCs on the top and 2000 at the bottom you get around 8um per ADC which is not much for a 12b SAR. This means the smallest capacitor values are probably pretty small and charge from the 12 switches could have a pretty large impact.

 

[Pierrot Lafouine]

sensors and adc converter

You can read this :
**broken link removed**
EDN january 22nd 2009
It wont answer INL/DNL question, but its good to know what is the state of the art in industry

Cheers!