System Design specs must create specs top-down or bottom-up for ACQ stability in terms of both Analog and Digital domain errors from DC to the Nyquist rate in both phase and amplitude of spectral domains and timing domain errors including; above slew rate, excess settling time, excess group delay, and noise interference.
Analog performance must have system design specs from bottom-up specs for an "Optimal Receiver" and top-down limits from ADC specs and > 400 Mbps LVDS timing.
If this were a parallel output, the timing might be trivial, but with serial LVDS and size reduction, the added complexity requires a skewed sync'd analog/digital state machine.
I believe that the ACQ+ edge must be more stable than an analog LO SNR using direct conversion. In the SDR system design, the phase noise spectral envelope must be defined to define the required ACQ jitter. This would exclude an FPGA ACQ design as warned on p19 CNV timing and implies a stable synchronous state machine is needed. I expect this requires a 15 MHz VTCXO with a full environment spec < 1ppm and low phase noise to match the 66.6 ns CNV+ timing and not the typical uC XO. The CNV- occurs in the middle of the last bit D0 being transferred at> 400 Mbps. This is needed to guarantee the last bit is transferred with adequate slack time for the next stable ACQ+ pulse. One may evaluate if these 2 clocks must be phase sync'd or not. Even though 18 bits every 15MHz needs > 270 MHz , tACQ = 66.6 - 39 = 27.7 ns
Concern over "CNV interval;63ns max. With a typical acquisition time of 27.7ns."
This ACQ time is the Analog period for tracking a new value which does not exceed the Slew Rate spec. and the CNV triggers a Hold {t
AP} in 0 time. {track & hold} vs {sample and hold}
My previous answer implies there is 3.6 ns min. of margin below 66.6ns. for the LVDS signals to achieve this 15 MHz sample rate with up to >400 MHz LVDS ACQ burst data transfer.
You have 27 ns of analog capture time to ensure your Optimal Receiver design specs have signal conditioners that do not degrade group delay, yet protect dV/dt from interference with ESD diodes which add 2pF of capacitance and have a channel BW that does not exceed the Nyquist BW not just at -3dB but your tolerance -x dB for SNR and error rate tolerance .
The CNV timing must be as precise as a LO phase noise to have as good a performance as traditional Analog radios. { or better if desired}
I would consult with any
Eval board guidelines and make no deviations without understanding the consequences.