AD9226 adc not working when "clock stabilizer" pin is used

[Georgy.Moshkin]

I have a design where AD9226 is used, and both experiencing similar problem:
when
1) MODE pin open: works (in this case "clock stabilizer" is disabled)
2) MODE to 5V: not working properly, distorted/scaled signal. Signal is scaled non-linearly depending on amplitude.
3) MODE to GND: not working properly, digitized data is zero

observed some strange voltage changes on noise reduction pins CAPB/CAPT
1) MODE pin open: CAPB=2.04V CAPT=3.08V (VREF=1.04V)
2) MODE pin to 5V: CAPB=3.72V CAPT=4.72V (VREF=1.04V) - this may explain why signal is distorted and "scaled"
3) MODE pin to GND: CAPB=0V CAPT=1.2V (VREF=1.04V) - here digitized signal shows only zero data
in my opinion clock stabilizer pin should not pull CAPB/CAPT voltages, although it may be normal.

Using schematic from datasheet fig5.a single ended input, common mode voltage = 1v.

 

[KlausST]

Hi,

how does your clock signal look like?
* is it continous and the frequency stable with stable duty cycle?

--> A scope picture is helpful.

Also the PCB layout critical.
--> show us your PCB layout.

Klaus

 

[FvM]

in my opinion clock stabilizer pin should not pull CAPB/CAPT voltages, although it may be normal.

It should not. There seems to be something wrong with other external connections of the ADC, a problem not yet addressed in your post. CAPB/CAPT voltage can be varied through SENSE and VREF, but should be symmetrical to 2.5V.

 

[Georgy.Moshkin]

Previously I have asked this question at
https://ez.analog.com/data_converte...uring-span-is-0-1v-when-vref-1v/322950#322950

KlausST, I had concerns about clock signal (I have used 40MHz from 3.3v microcontroller, and it looked not very good on a scope).
But the same behavior is observed with lowered frequency, for example 4MHz, when clock signal have very clean 3.3vpp.
I thought maybe 3.3v clock may be the problem, but from topic on ez.analog.com and datasheet it seems to be ok.

FvM, here are some images:

Photo of previous prototype (mode pin bent to make it work)


Current prototype, as advised on ez.analog.com, i use exact schematic from datasheet, but without tantalum caps (tried small black tantalum caps on photo above without any effect, recommended capacity). So now using schematic from datasheet:


New layout:


New schematic (5v looks like not connected, but my nets are connected by name)
On the right there is vref connection to blue "BUS", not connected to any circuits outside while testing problem with "stabilizer pin"


highlighted 5v connections:


0ohm resistors to choose mode and value of internal vref

To be sure i tested it without anything other soldered: only MCU with ADC. No opamps or other ICs.

 

[KlausST]

Re: AD9226 adc not working when "clock stabilizer" pin is used

Hi,

(Look at my post#2l
We still can't verify your clock signal.
We just know it is 3.3Vpp, but we still don't know about waveform, duty cycle, stability...and whether it is continous or not...

Similar with the PCB layout.
Here we can't verfy if you used split GND planes for analog and digital.

But we can see that you joined AVDD with DRVDD.
With most ADC they are separate not to introduce noise from the "dirty" digital part to the "clean" analog part.
--> separate them and use at least proper filtering for the analog part

Klaus

- - - Updated - - -

Added....

What's the use of the 33Ohms resistor in the CLK line?

Datasheet:
I just recognized the weird naming of the data lines.
Not only that it starts with 1 and counts up to 12....
...but the most (beep) issue is that bit1 = MSB and bit12 = LSB.

Klaus

 

[FvM]

As long as the internal reference voltage circuit doesn't work (as the reported CAPB/CAPT voltages indicate), you don't need to wonder about implausible output codes or think about signal quality. As far as I'm aware of, the reference circuit doesn't depend on clock signal quality, there must be a more basic problem. I must confess that I never observed a similar problem with 3V and 1.8V ADI converters, they have quite similar mode selection circuit, never used a 5V type.

Regarding clock stabilizer usage, it's meaningful if you can't provide stable near 50% duty cycle clock. Can you operate the circuit without clock stabilizer? To verify if the problem might be related to clock signal quality though, can you check if the CAPB/CAPT voltages change when stop the clock?

 

[Georgy.Moshkin]

FvM, i use it without clock stabilizer all this time.
I tried to stop clock and do not see any changes in capb/capt (still strangely pulled when mode pin is tied to gnd or 5v)

Now I am thinking to try following:
1) providing 5v clock signal
2) buying some pcb with AD9226 which works with mode pin. Then unsolder AD9226 and replace it with those i have already bought
3) buying few samples from a bigger components supplier


KlausST, yes, bit order is reversed.
Currently i only have 50MHz scope, and it seems not enough to measure clock signal.

Problem reproducible at any sampling frequencies. I tried 9MHz clock and mode pin still causes problems if tied to gnd/5v:



I am pretty sure it does not miss pulses or something like that. Although I did not do strict measurements, maybe need to learn more about using digital features of oscilloscope.

33 ohm resistor on clock pin is for tuning clock waveform, for 65mhz i used 0ohm.

Layout:



I usually use solid ground plane everywhere, and 0 ohm resistor as jumpers.