It's likely that the signal will "pump" the Vdd rail through the
ESD protection network. Whether that bothers the part, comes
down to current limiting and reliable pin current max rating.
But you can't believe datasheets about that, because such
ratings often are set by powered pin induced electrical latchup
triggering (plus a bunch of sandbagging).
If you can stand it, putting a series resistor that meets those
specs (input pin max current) given signal V and the R will
keep you on the right side of single pin destructive effects.
What might ensue from half-@ss-powering a controller, is
another matter. A series input R, and either natural supply
load or adding some, or ensuring that (say) a master reset
pin must follow your DIP-switch disable (not likely true for
a simple POR, if supply is lifting up) might solve that. Might
think about whether there's an elegant scheme, like DIP
switch controls both a "load switch" (power) and hits the
main RSTb to ensure known behavior.