Active and inactive dummy transistors in the matched array transistors

[Junus2012]

Dear friends,

below are the suggeted three connection of dummy transistors to the cascoded circuit.

In the first two schemes the dummy transistors are off as thier VGS tied to zero. However,

in scheme 1, the drain of the dummy transistors are connected to the drain of the matched transistors. Thus it adds parasatic capacitance. This procedure I followed here in this formum as was suggested that dummy transistors better to share net with the matched array. I dont understand why shoud be ?

Therefore, I tried to plot scheme 2 where dummy transistors share nothing with the matched array, all the terminals are tied to ground , NMOS is off and no issue should be. Here must be no load effect on the matched array, and in my opinion it should be better, but I need your point of view please.

in the last scheme 3, that is from Allen Holberg, he shared the gate between dummy and the matched array, in my opinion it will be rise the Cox so it increase the parasatic capacitnace more than scheme 1.


Finally, Cadence bring my attension when I am learning to put dummy from MODGEN. he was giving two options, active dummy which is connected to a net or inactive, and I think I provided both in the presented schemes.

Looking forward to your discussion

Best Regards

 

[sutapanaki]

You need to have a common net between the dummy and the active transistors, because the dummies need to be in the same OD as the active MOS. But having a common node doesn't necessarily mean having a common drain. You may have common ground node for active and dummy. I don't like scheme 1 because it loads the cascode node. Scheme 2 is not good for the cascode devices because they don connect to ground. Scheme 3 is OK, especially if you lay out M1-M3 as one cell, then you just use a similar cell for the dummy. Since in what you show the gates are biased, that is they are ac ground, then extra caps there will not hurt.

 

[Junus2012]

You need to have a common net between the dummy and the active transistors, because the dummies need to be in the same OD as the active MOS. But having a common node doesn't necessarily mean having a common drain. You may have common ground node for active and dummy. I don't like scheme 1 because it loads the cascode node. Scheme 2 is not good for the cascode devices because they don connect to ground. Scheme 3 is OK, especially if you lay out M1-M3 as one cell, then you just use a similar cell for the dummy. Since in what you show the gates are biased, that is they are ac ground, then extra caps there will not hurt.

Dear Suta,
Thank you for the reply,

Actually I didnt understand what you mean by "dummies need to be in the same OD as the active MOS" ?

It means in scheme 2, the down transistors are ok for the dummy, but the cascode is not good because they dont share the ground, again asking you please what will be the effect ?

in the third scheme suppose I have cascode mirror with no biasing voltage, still, you say it is good ?

 

[sutapanaki]

Same OD means you put the active and dummy transistors in the same diffusion. I suppose you lay them out with fingers and something like S-D-S-D-S. If this is the case then you need to have a common node between active and dummy devices. If you lay them as separate devices, each in its own diffusion, then you don't really need common node.

 

[Junus2012]

Same OD means you put the active and dummy transistors in the same diffusion. I suppose you lay them out with fingers and something like S-D-S-D-S. If this is the case then you need to have a common node between active and dummy devices. If you lay them as separate devices, each in its own diffusion, then you don't really need common node.

Ok I got your point now,

that is hy you said in the second scheme the down transistors have no problem as they share the ground mean they share the source which helps me to make them in the same structure like S-D-S-D-S, that is clear

in the cascoded transistors in scheme 2 here the dummies can not share the same OD... that is why you didnt like the dummy of the cascoded transistors in scheme 2.

However, if you come to the scheme 3 from Holberg, you see that dummies are not sharing a drain or source so basically you cannot them in the same OD, hence the dummy will be aside seperated, if this is a problem why you liked the scheme 3 ? sharing the gate will not allow them to be in the same ODD as they dont have a common source or drain ?

and by the way is there a problem if dummy is not merged with the same OD of the matched transistors, may be you mean that transistors at the end will have different surrounding from the middle transistors.

Just please one more thing, for me I am not matching the four transistors of the cascoded transistors together, I am matching the two down indivisually from the upper cascaded one.

Thank you again

 

[sutapanaki]

Scheme 3 only works well if you combine for example M1-M3 in a cell and abut them - for example you have one finger of M1, say S-D and then 1 finger of M3 like S-D and you abut them so it becomes S-D-S-D. And then you repeat that structure, maybe flipped so it can abut. Then at the end you place a dummy or two and the dummy follows the same structure but gate grounded. That suggests that the W of the cascode finger is the same as the W of the bottom transistor. Just one of the possible ways to lay out cascoded
transistors.
I think it makes less sense to not merge the dummies in the same OD. Dummies are there to prevent edge effects and if you not merge it, then you still see the edge effects. What I just said is not valid in the case of laying out the individual transistors in their own OD. Then each finger of the transistor is a device by itself in its own diffusion and the dummy just repeats that strategy being in a separate not merged OD. But probably this is not very area efficient.

 

[Junus2012]

Dear Suta,

Thank you for your help,

So you are suggesting to modefy scheme 3 by connecting the gate to the ground and not sharing it with the array gate transistors as proposed by holberg in the shown image. However, still importnat thing is missing that dummy transistors of the cascoded transistors are not sharing drain or source with the matched transistors, so still I can not abute them in the same OD regardless talking about the gate connection

secondly please,

Assume I am laying out the down two transistors seperately from the cascoded devices, for the down transistors I will put the dummy transistors as shown in scheme 2 which also approved by you, now can you please suggest me a bout the how to connect the cascode transistors dummies ?

it will be very kind of you if you could plot it

thanks

 

[sutapanaki]

Dear Suta,

Thank you for your help,

So you are suggesting to modefy scheme 3 by connecting the gate to the ground and not sharing it with the array gate transistors as proposed by holberg in the shown image. However, still importnat thing is missing that dummy transistors of the cascoded transistors are not sharing drain or source with the matched transistors, so still I can not abute them in the same OD regardless talking about the gate connection

You can still share the drains and connect the gates to ground. Why not. That should be a perfectly legitimate way to do it.

secondly please,

Assume I am laying out the down two transistors seperately from the cascoded devices, for the down transistors I will put the dummy transistors as shown in scheme 2 which also approved by you, now can you please suggest me a bout the how to connect the cascode transistors dummies ?

it will be very kind of you if you could plot it

thanks

Yes, for the bottom transistors. For the cascodes the dummies have to share the drain or source and have the gate to ground.

 

[Junus2012]

Dear Suta,

Speaking only about the cascoded transistors which I am going to match them alone, below you see the array plan of the matched transistors,



as you see since these transistors dont have a shared drain or source so I can abute them in one OD, sure every transistor has to be sepertaed from the other.

Now talking about the dummy of this array, if as you suggested to put a dummy to share the drain or the source, let me say the source , then ideally every transistor in this array must have two dummied, one in the right and one in the lift to make the array equal ... this will increase the total size .

However, if I use a dummy transistor with gate, source and drain connected to ground , then simply I can distribute the a the end of the array as shown below



Hence in the array above there wil be no need to share a node

can you please confirm it to me
thank you once again

 

[sutapanaki]

This is a one possible layout. Or you can put all of M3 in one OD and all of M4 in another and don't interdigitize or common-centroid M3 and M4. Then you can have one dummy that bridges the two branches - from the drain of M3 to the drain of M4 and connect the gate of the dummy to ground. And you can put also dummies on the other sides. These are cascode devices and you don't really need super matching for them that will justify the use of common-centroid layout.