Accumulation varactor layout

[mazelk]

varactor layout

Hi...

How can I fix AMOS (accumulation MOS) - varactor's variables design to reach a minimun and maximun capacitance ?

How can I layout this device ?

I heard about split layout varactor into "rows" and "columns". Why ?

Best Regards

 

[sunking]

accumulation varactor

it is more like an analog circuit design.
pay attention to that the body contact to SD. This is to say,
|
-----------
-----------------------
| | |
| | |
-|-------|---------|--

SBD contact together.

And make sure Vgs<<Vth

 

[franck]

mos accumulation varactor design

"
|
-----------
-----------------------
| | |
| | |
-|-------|---------|--
"

???????????????????

 

[hrkhari]

use of accumulation capacitance

Hi:

The maximum and minimum value of A-MOS could be determined by performing S-Parameter analysis for a given dimension. The imaginary portion is proportional to the capacitance of the A-MOS, for a given Vc.

The purpose of splitting the layout into number of rows and columns is to reduce the gate resistance of the varactor, due to its significant contribution to phase noise. Hope this helps

Rgds

 

[mazelk]

varactor layout and quality factor

Modifying geometry, only change max. and min. capacitance values, also quality factor.

does exists any way to change C-V slope for accumulation varactor ??

I want to decrease its slope, because the gain of linear region is so high, and very small signal would be enough to change capacitance a lot, maybe undesirabilly.

 

[pk3316]

accumulation mos

To reduce CV slope, paralell some fixed capacitor to varactor, but the tuning range of capacitance will be reduced also. Sweep the the length and width of one finger varactor may help you to findout a good area for it, also the bias voltage of source drain has effect on the tuning curve