abs(complex_number) in Digital Logic?

Hi,

I am interested in knowing how the absolute value of a complex number can be found using digital logic design.

I know that abs(x+iy) = sqrt(x^2 + y^2).

Is there any easy way to implement it in Verilog or VHDL?

The expression looks quite straightforward, isn't it? Obviously it involves a squareroot calculation. If it can be easily implemnted is a matter of number formats and intended accuracy. You might consider e.g. a look-up table with interpolation.

Thanks FvM for your quick reply.

FvM said:

Obviously it involves a squareroot calculation

Click to expand...

That's my problem. I am a beginner and I don't know know how to implement square root logic.

FvM said:

If it can be easily implemnted is a matter of number formats

Click to expand...

My inputs are 14-bits in 2.12 format.
If squared, then they become 28 bits each. And then a square root has to be applied. I am bit confused in determining the number of bits.
Can you please explain how to calcuate the number of output bits for the absolute function?

v_suma said:

That's my problem. I am a beginner and I don't know know how to implement square root logic.

Click to expand...

Easiest way is to use an IP core provided by your chosen vendor. Writing your own would just be like re-inventing the wheel (and you wouldnt be the first or last)

My inputs are 14-bits in 2.12 format.
If squared, then they become 28 bits each. And then a square root has to be applied. I am bit confused in determining the number of bits.
Can you please explain how to calcuate the number of output bits for the absolute function?

Click to expand...

You're never going to get perfect square root, you just specifiy the number of resulting bits you want/need. The IP cores give you a Q output and remainder value, with remainder determined by the number of bits in Q.