Kicchan
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I am using Cadence Abstract Generator to generate the LEF file of a macrocell (full custom) which I want to put along with another one (standard cell) inside my chip.
My full custom macrocell is made up of hundreds of cells (basic gates and FFs) and has a size of around 900 x 330 um2.
When I run the abstract step for my macrocell in Abstract Generator I get the following warning:
ABS-907: Cell FC_8ch: net VDD has full shape pin geometry that violates the minimum area rules set in the technology file
ABS-907: Cell FC_8ch: net GND has full shape pin geometry that violates the minimum area rules set in the technology file
On Cadence Abstrac Generator User Guide it's written:
ABS-907: ABS_NET_HAS_FULL_SHAPE_PIN_MAR_VIOLATIONS
Message Text: Cell %: net % has full shape pin geometry that violates the minimum area
rules set in the technology file.
Additional Information: Pin geometry for a layer must adhere to the minimum area rules
defined for that layer in the technology file. If full geometry extraction is performed, and the
pin still did not satisfy minimum area rules, this indicates a significant problem in the layout
design.
I tried incrementing the pin size but still get the same warning.
Does anyone know how to fix this problem? Is it wrong generating the LEF file while keeping the warning?
My full custom macrocell is made up of hundreds of cells (basic gates and FFs) and has a size of around 900 x 330 um2.
When I run the abstract step for my macrocell in Abstract Generator I get the following warning:
ABS-907: Cell FC_8ch: net VDD has full shape pin geometry that violates the minimum area rules set in the technology file
ABS-907: Cell FC_8ch: net GND has full shape pin geometry that violates the minimum area rules set in the technology file
On Cadence Abstrac Generator User Guide it's written:
ABS-907: ABS_NET_HAS_FULL_SHAPE_PIN_MAR_VIOLATIONS
Message Text: Cell %: net % has full shape pin geometry that violates the minimum area
rules set in the technology file.
Additional Information: Pin geometry for a layer must adhere to the minimum area rules
defined for that layer in the technology file. If full geometry extraction is performed, and the
pin still did not satisfy minimum area rules, this indicates a significant problem in the layout
design.
I tried incrementing the pin size but still get the same warning.
Does anyone know how to fix this problem? Is it wrong generating the LEF file while keeping the warning?