about warning messages in xilinx

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kannan2590

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Found area constraint ratio of 100 (+ 5) on block iqmap12, actual ratio is 36.what this warning message tell.i could not understand the meaning of this warning.i am using vertex 4 fpga and whether this message effect the final output of the fpga .
 

I see this message all the time. I ignore it, since the design places and subsequently routes with no timing violations (also works in the system).

Xilinx should really get rid of these useless (probably useful for Xilinx) for the end user warning/information messages.
 

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