Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

About voltage doops of the S/H @ hold phase

Status
Not open for further replies.
A

analogman

Junior Member level 1
Junior Member level 1
Joined
Nov 28, 2004
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
219
Hello.

I am designing the S/H circuit.
But, I have a trouble now.

In hold phase, the holded voltage is drooping!
Is it natural ? I think it causes less acurate...
I use 250fF for sampling cap.

There is no teacher to advise me.
Any advise or solution, please.
Thank you ...
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top