about vhdl code for feedback loop

[kannan2590]

I suggest finding a good VHDL tutorial and working your way through it. You clearly have no idea what you're doing.

I have tried with good vhdl books and i have also tried your code .But the problem is the output of the feedback circuit is showing undefined.I have only asked if at all there is any mistake in the vhdl testbench in declaring the xin values then tell me the mistake.In books i have never found out how to declare xin or din values or vhdl tutorials as you have mentioned.

 

[TrickyDicky]

When you post the code you're testing, then we can comment on it. You cannot be using the last code you posted because it has errors.

So please post the code you are simulating.

 

[pkmads]

l1: for t in 0 to 79 loop
if( 0 <= t <= 19) then
k<=k0;
elsif(20 <= t <= 39) then
k<=k1;
elsif(40 <= t <= 59) then
k<=k2;
else
k<=k3;
end if;
is this correct in vhdl

 

[FvM]

As a delayed comment on the post #13 testbench, besides possible problems in the corrected DUT code that hasn't been shown, the testbench misses to assert the reset signal. So unless the DUT uses an initializing statement, the accumulator register will be never reset.

P.S.:

is this correct in vhdl

Clearly no.

Please observe forum rules: "Don't intrude in threads with different subject"