I think your situation is
1. RTL sim passes.
2. Gate sim with no timing passes.
3. Gate sim with timing (SDF backannotate) fails.
To Do:
1. You should make sure no timing violation in DC report.
2. Debug your netlist with SDF backannotated, check if there is any timing violation report in simulation report file.
3. Compare all top module inputs waveform in timing/none timing. Make sure they are the same.
4. If you want dig through netlist with SDF file. Use GOF from
www.nandigits.com
GOF can load netlist and SDF file, and isolate the gates you have interest in, and even report the timing between connections and gate delay.
Hope it helps.
Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.
Added after 13 minutes:
I think your situation is
1. RTL sim passes.
2. Gate sim with no timing passes.
3. Gate sim with timing (SDF backannotate) fails.
To Do:
1. You should make sure no timing violation in DC report.
2. Debug your netlist with SDF backannotated, check if there is any timing violation report in simulation report file.
3. Compare all top module inputs waveform in timing/none timing. Make sure they are the same.
4. If you want dig through netlist with SDF file. Use GOF from
www.nandigits.com
GOF can load netlist and SDF file, and isolate the gates you have interest in, and even report the timing between connections and gate delay.
Hope it helps.
Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.