about timing corner question

[owen_li]

Hi

when I do STA for our chip, I have some question about the timing corner.

For example, the supply voltage for our chip is 0.9v, the setup corner to fix worst setup timing is ss0p81v

the hold corner to fix worst hold timing is ff0p99v

I found these two voltage both has 10% lesser or greater than supply voltage.

I want to know why. Also why choose 10% difference , not 5%, or other voltage.

Thanks very much!

 

[asic_service]

I think this is just an industry stander. We can define it at 5% difference.
But 5% difference will be more difficult to meet as there are some variations: power supply, IR drop.
So, this may cause additional cost to meet this requirement.

 

[mail4idle2]

According to Fabrication standards, the voltage seen by a gate in wafer can range between +10% of the required actual voltage.

 

[owen_li]

According to Fabrication standards, the voltage seen by a gate in wafer can range between +10% of the required actual voltage.

So, Do you mean it is related to IR drop of the power network ?

If IR drop of our chip is more than 10%, Is the sta corner much more optimistic ?

 

[Prashanthanilm]

Yes, It is Fabrication standard value.

Can put in this way also: Due to metal routing (ie..Resistance path), there is a drop of some voltage level.
So, even though the VDD=0.9V, the source will get around 0.895V . The +/- 10% will take care of this issue.

 

[kumar_eee]

Usually, we perform the IR-Drop Analysis with 10% variation and this is mainly due to the libraries are characterized with +/- 10% of VDD.

This is mainly to account the variations in actual silicon.

 

[owen_li]

Usually, we perform the IR-Drop Analysis with 10% variation and this is mainly due to the libraries are characterized with +/- 10% of VDD.

This is mainly to account the variations in actual silicon.

Thanks for your reply, kumar!

I have another concern.

The IR drop usually contributes a voltage on gate less than supply voltage of the chip.

So why do we also should analyze the timing on the +10% voltage of the supply voltage ?

I mean the hold timin corner of ff0p99v, if the typical supply votage is 0p9v.

Thanks!