I am a new guy in this forum. Now I simulate start-up function of a bias circuit (Vt reference) for OP by transient simulation.
And I found that the result has relation to the incremental time scale I set. For larger value, the bias circuit "start-up" even though I remove the "start-up" circuit.
Why? What is this time value you usually set?
to check startup, normally, u should prebiased the node to either low/high using 1G resistor, so that the node cause the bias circuit to stay off.
Using a larger time scale causes the simulator to miss details, when it see no transition, it would jump a bigger time step than if u have a smaller time scale. However, this should bear no direct consequence on whether your circuit start up or not. Did you initiate the nodes?
Definately, you can set up the initial condition. Usually the circuit which needs a start up has two stable operating conditions, one at zero volts and the other at the normal voltage at which the circuit operates. Hence, the start up is used to push the circuit to the second stable operating condition by pumping the required current. So, you can set one of the voltages as initial operating condition(most preferbly zero volts)
Yes. To check whether the start-up circuit can function or not, first you have to set the bias circuit stay off state, right? One more thing, simulate different ramp rates and different corners/temperature etc. to make sure it does work.
to check startup, normally, u should prebiased the node to either low/high using 1G resistor, so that the node cause the bias circuit to stay off.
Using a larger time scale causes the simulator to miss details, when it see no transition, it would jump a bigger time step than if u have a smaller time scale. However, this should bear no direct consequence on whether your circuit start up or not. Did you initiate the nodes?
Now I simulate the start-up function as this figure shows. Bias circuit is a Vt-reference bias circuit. Transistor MS (act like a power down switch) is used to set the initial condition for the p-NMOS current mirror. And Vdd is always high.
But I still have a problem. The response still has relationship with the timestep value. It "start-up" even I remove the "start-up" circuit for timestep=0.1n. Is 0.1n still too large?
Smaller timestep should be more correct. But how small? It disturbs me so much.
Normally 0.1 ns is good enough to characterize. In reality you do not ramp up the supplies so fast. But, in case, you still have doubts do go for a smaller time step.