Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The INL and DNL are parameters that characterize the deviation on the code transition voltages of the ADCs. On the laboratory this is measured using the histogram method, which is a statistical method. However this requires a large number of samples – to use this method your simulation would take a LOT of time.
So, I guess that the best option is to put a slow ramp at the input and determine the input voltage where each code transition occurs. But note two things:
1. The ramp must be really slow, if you want to have a decent measurement accuracy. For example, if you want to have a resolution of 0.1 LSB in your measurements, the input voltage must take 10 clk cycles to increase one LSB. For a 10-bit converter you need a simulation with 10*1024=10240 clk cycles, which still results in a rather large simulation.
2. If you want to have realistic results, your simulation must include device mismatches; otherwise you can get almost ideal results in the simulation and bad results in silicon.
An option usually used is to build a model of the ADC (usually in MATLAB or C), which is much faster to evaluate. However, to do this you must model the non-idealities of each block of the ADC. You MUST have a very deep insight on your ADC’s architecture and on each blocks’ limitations.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
