gaom9
Full Member level 4
set_test_point_element
Hi,
I met a question in my design of DFT for a SOC chip. In this SOC, there are PLL and many memory modules. I want to bypass the memory when testing, so I change the RTL code to add a bypass function to them, but I find this method does not work.
In RTL code, I added a mux which is controlled by the test_en signal of the chip to every memory, and than in the DFT compiler, I add the definition as follow:
set_dft_signal -view existing_dft -type ScanClock -timing {4 5} -port clk
set_dft_signal -view existing_dft -type Reset -active_state 0 -port reset
set_dft_signal -view spec -type ScanEnable -active_state 1 -hookup_pin [get_pins u1/C] -port test_en
set_dft_signal -view existing_dft -type Constant -active_state 1 -port TEST_MODE
and I added a TEST_MODE signal to it. The coverage_estimate before adding the bypass function is 84.32% and the violation is all about the memory; The coverage_estimate after adding the bypass function is 89.02%(but all the violations are still there...). I think is the bypass function does not work when testing? If it works, the coverage_estimate will be much higher I think.
My question are:
1, how to implement the bypass function in DFT, changing the RTL code or any other method? which signal should I used to controled it, test_en or TEST_MODE...?
2, how to make the DFT compiler know the bypass function added by changing the RTL code when do the DFT compile?
And other question, I found this warning in the DFT reports：
Warning: Port 'reset' cannot be used as a scan port. It has been previously inferred as an asynchronous signal. (TEST-337)
This reset port is used in the RTL code, and when DFT, it is reused as the RESET signal. I found this warning comes out when define a new port for RESET or reuse the port in DFT compiler. Does it do harm to our design, please?
Thank you.
Best regard!
Hi,
I met a question in my design of DFT for a SOC chip. In this SOC, there are PLL and many memory modules. I want to bypass the memory when testing, so I change the RTL code to add a bypass function to them, but I find this method does not work.
In RTL code, I added a mux which is controlled by the test_en signal of the chip to every memory, and than in the DFT compiler, I add the definition as follow:
set_dft_signal -view existing_dft -type ScanClock -timing {4 5} -port clk
set_dft_signal -view existing_dft -type Reset -active_state 0 -port reset
set_dft_signal -view spec -type ScanEnable -active_state 1 -hookup_pin [get_pins u1/C] -port test_en
set_dft_signal -view existing_dft -type Constant -active_state 1 -port TEST_MODE
and I added a TEST_MODE signal to it. The coverage_estimate before adding the bypass function is 84.32% and the violation is all about the memory; The coverage_estimate after adding the bypass function is 89.02%(but all the violations are still there...). I think is the bypass function does not work when testing? If it works, the coverage_estimate will be much higher I think.
My question are:
1, how to implement the bypass function in DFT, changing the RTL code or any other method? which signal should I used to controled it, test_en or TEST_MODE...?
2, how to make the DFT compiler know the bypass function added by changing the RTL code when do the DFT compile?
And other question, I found this warning in the DFT reports：
Warning: Port 'reset' cannot be used as a scan port. It has been previously inferred as an asynchronous signal. (TEST-337)
This reset port is used in the RTL code, and when DFT, it is reused as the RESET signal. I found this warning comes out when define a new port for RESET or reuse the port in DFT compiler. Does it do harm to our design, please?
Thank you.
Best regard!