About the boost PWM DCDC stability

[fantaci]

What is effect if the output ripple does not been well filtered by compensation network?
I mean the DCDC modulator module is only suitable for low freqency analysis, when the frequency extent to clock frequency, how to analyze the effect of output ripple.

 

[smyback]

Switching Regulators (DC-DC converters) always have significant output ripple and usually employ an additional output filtering stage, but are usually much more power-conversion efficient than an equivalent Linear Regulator.

Digital circuitry has a higher level of voltage supply noise immunity than an analogue circuit. So a Switching regulator with additional output filtering is usually fine in digital applications. Take a look at a Personal Computer!

Analogue circuitry will be much less tolerant. Especially audio circuitry, where you will always hear the switching "hum" in the speakers. Personal Computer Sound Cards have their own linear regulators which step down the 12V PC supply (which is much less noisy that the 5V or 3.3V lines) to drive the audio circuitry.

So in summary, a second stage of output filtering added to a switching regulator is usually sufficient when driving digital circuitry, but when driving noise sensitive analogue circuitry it is best to add an additional Linear Post-Regulator (and if you are concerned about preserving power conversion efficiency, it should be a Low-Dropout type).

All power supplies should be designed to minimise output noise from the start, the limiting factor being first the specification for the supply and then the component count/cost. Also each "analogue circuit module" and each IC in the circuits to be supplied should have its own power supply filtering capacitor(s) mounted close by.

When choosing a filtering capacitor(s), remember to consider what frequency range you need to filter versus the Self Resonant Frequency and Equivalent Series Resistance (parasitics) of the capacitors you are choosing.

It is of course sensible to perform a time domain simulation of the Switching Regulator by itself, and the accuracy of such a simulation depends on the accuracy of the component models and parasitics. You should make note of the frequency and level of the output ripple. You can also try to determine the output resistance of the regulator. This information can then be used to determine a "simplified model" of the Switching Regulator composed of a DC source plus AC source "approximation" of the output ripple plus an output resistance.

The "simplified model" of the Switching Regulator can then be used to replace the "ideal battery" in the simulation of the circuit to be supplied. This will make the simulation run much more quickly and still provide a good approximation of the effect of supply noise.

If you really want to get pedantic you can do an FFT on the Switching Regulator output and note the frequency and levels of the output ripple and its harmonics and use multiple AC sources in the "simplified model" for each significant harmonic.

Hope this helps.

 

[fantaci]

Your advice is valuable. Thanks to you.
But, I am sorry I did not make my discription clear. The ouput ripple will feedback to the DCDC error AMP and thus couple with SAW-TOOTH wave in the chip. Does this couple has any effect with the performance of DCDC modulator such as stability?
In my case I observed some small low frequency regular ripple(Much low than clock frequency). I test the loop gain of this chip, it at least has 50 degree phase margin, So I do not know why this small `unstability` happened. Does it come from noise coupled with SAW-TOOTH wave? This low frequency is around 10mV compared to 15V output.

 

[smyback]

You have a problem with low frequency oscillation on the output of a PWM Boost Converter? I'm sorry too, I should have paid closer attention to the question.

Have you checked the loop bandwidth to ensure that it is less than half the switching frequency? Otherwise it will try to respond to its own switching ripple and oscillate.

Maybe this time I have helped?

 

[fantaci]

You have a problem with low frequency oscillation on the output of a PWM Boost Converter? I'm sorry too, I should have paid closer attention to the question.

Have you checked the loop bandwidth to ensure that it is less than half the switching frequency? Otherwise it will try to respond to its own switching ripple and oscillate.

Maybe this time I have helped?

No. the bandwidth is low enough compared to clock frequency. Anyway, it is not a problem any more. The problem is the test method. when using FET prob, this phenomina vanished.

 

[VVV]

The bandwidth of the control loop must be less than half the switching frequency. That is because the switching regulator is in essence a sampled-data system, so Shannon's theorem applies.

For acceptable performance however, the bandwidth should be at least 4-5 times lower than the switching (ripple) frequency. So the ripple will not have any effect on the control loop. In fact, the bandwidth of the loop is much lower than that in today's high-frequency converters. You can have the DC/DC controller running at 1MHz or more, but the control loop can have a bandwidth of only a few tenths of kHz.