About step change in the output of SC circuits

[hr_rezaee]

Dear All
Hi
I need some papers or books about step change in the output of SC circuit (for example MDAC of pipeline ADC) in the direction of opposite to its final value.
I need proof of it.
regards

 

[safwatonline]

maybe u should post the circuit and the test bench.

 

[hr_rezaee]

Hi
Thanks
I mean theoretical proof for step change in the output of SC circuits.
I have one in this paper but I need better one.

 

[mitgrace]

Dear Sir :
What is your mean ? the S.C output is evaluation. You must see DAC output (reference circuit) , it is settling . The almoset key is here. But there are few papers discuss it.

 

[hr_rezaee]

Hi
there is an proof for step changes at the start of charge transfer phase in some SC circuits such as SC amplifier.
see these figs and above attached paper.

Now, I need another paper or book that discaused about this phenomenon.
I need better mathematical proof for it.
best regards

 

[lladnar23]

Yea, so it's just a capacitive divider involving the feedback capacitor (CF) and the load capacitor (CL). Let me illustrate with a simple example. Consider an inverting stage with a gain of -2, and your feedback capacitor is 1/10 the size of your load capacitor. Now lets say we apply a -1V step input. There are two things that occur. First, we have a step change at the output due to the capacitive divider CF/CL. The output sees a negative step of Vin*CF/CL. For our numbers that's -1V*1/10 = -0.1V. Next, we have the settling of the stage, and it will settle to 2*Vin = +2V. So you can see that initially the output goes negative, then it eventually settles to the positive value as we expected.

 

[hr_rezaee]

Dear lladnar23
Thanks
It is true. but I can't understand why we use step as input?
can you explain about step input in for example S/H circuit or Gain stage ?
Best regards

 

[zawmintun1]

Thank

Added after 3 minutes:

0.52

 

[lladnar23]

Well, since it's a switched capacitor circuit, we are sampling some voltage in clock phase 1, then when clock phase 2 happens, we apply the sampling cap to the virtual ground node of the opamp -- that's basically a step change in voltage since the voltage on a cap can't change instantaneously (I=CV').

 

[northeast1]

Dear All
Hi
I need some papers or books about step change in the output of SC circuit (for example MDAC of pipeline ADC) in the direction of opposite to its final value.
I need proof of it.
regards

you can refer to the op amp design.