About simple RC circuit...

Hi,

can anyone help to analyze the circuit shown below?
The clock is 10V : 50KHz signal. What I was thinking is because of the series resistors, Capacitor should charge up 5V ( =10/2).

But when simulated, the voltage across capacitor settles at 2.5V with very small ripple. So can anyone explain why cap settles at 2.5V (not at 5V)?
I tried to analyze it but did not understand.




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Thanks.

I see, that you know how to operate a simulator. But did you ever study electronic circuits? I suggest chapter 16 RC AND L/R TIME CONSTANTS from Lessons in Electric Circuits Volume I - DC Lessons In Electric Circuits -- Volume I (DC) - Table of Contents

Please notice particularly the property Time Constant of an RC circuit. The shown waveform isn't correct by the way, the voltage rise will follow an exponential rather than linear function.

I think you didn't understand what I am asking or the circuit!
If we go with the RC circuit analysis, then the both resistor will divide the input voltage and the voltage across the capacitor is 5V, right?
so this mean, the capacitor should charge up to 5V.
my question is why it is not able to charge up to 5V, why it stables at 2.5V?


My input is clock signal see the attachment.

FvM is right, you are wrong!

You are forgetting the time constant. It would be 5V IF THE INPUT WAS DC, assuming the clock is a square wave, when clk is 10V, the capacitor charges, when it is 0V it discharges, the mean is 2.5V.

Brian.

correct. so this mean I should get the ripple which varies from 5V to 2.5V.
But its not, why so?

A casual view clarifies, that the pulse width of the square wave is only 1/40 of the RC time constant. So the capacitor voltage will only change by 1/40 of the input magnitude.

The additional point to be considered is the 1:1 voltage divider formed by the two resistors in your circuit. Thus the capacitor voltage will load to the average value observed after the voltage divider, which is 2.5V.

thought of it is as a voltage divider and the capacitor is connected across the resistor therefore it can go a maximum value of 5v if on for full 5 time constant (which in your case is 5 x 1 ms = 5ms) 1 time constant (1 ms) can charge it up to 63%. but your on pulse time is 10 us @50 Khz(assuming 50% duty cycle) thats why it is showing you 2.5 V which is the RMS value, actually will be varying slightly as the capacitor charges and discharges....

FvM said:

A casual view clarifies, that the pulse width of the square wave is only 1/40 of the RC time constant. So the capacitor voltage will only change by 1/40 of the input magnitude.

The additional point to be considered is the 1:1 voltage divider formed by the two resistors in your circuit. Thus the capacitor voltage will load to the average value observed after the voltage divider, which is 2.5V.

Click to expand...

As mentioned input clock frequency is 50KHz (=20us). I am a small kid in this field, so can you explain me how the pulse width is 1/40 of RC time constant?:?:

Back to basics....

Lets suppose the clock came from a switch and you controlled it manually. If you switched the input to ground, any charge on the capacitor would discharge through both resistors and the result would eventually be 0V across it.
Now change the switch so it sends 10V to the circuit, the two resistors will limit the maximum voltage to 5V because they form a potential divider, some extra current flows through the input resistor and charges the capacitor but after a short time, it reaches 5V and no more extra current flows.

So at slow switching speed, the voltage goes from 0V to 5V.

Now lets switch it faster. Up to a certain speed the charging and discharging lets the voltage rise to 5V and fall to 0V just like before but there comes a point where the switching is too fast for the capacitor to fully charge and discharge. Now the voltage doesn't have time to reach 5V before the input changes state so it reaches a voltage less than 5V, similarly, if the input changes to 10v before the capacitor has fully discharges, it will not go down to zero.

As the switch or clock signal gets faster and faster, the capacitor has even less time to charge and discharge, as some point the voltage across it looks almost constant. There will still be a small ripple in the voltage but at faster clock frequencies the ripple gets smaller and smaller. The voltage will be stable at around 2.5V if the input clock was a square wave.

If you do some research on "time constant" you will see there is relationship between the value of a capacitor and the speed it charges and discharges. No matter what value capacitor you use, there will be a clock frequency that lets the voltage average without much ripple. At higher frequencies, the capacitor doesn't need to be so large.

Brian.

betwixt said:

Back to basics....

some extra current flows through the input resistor and charges the capacitor but after a short time, it reaches 5V and no more extra current flows.

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Now the voltage doesn't have time to reach 5V before the input changes state so it reaches a voltage less than 5V.

*****************

The voltage will be stable at around 2.5V if the input clock was a square wave.

Brian.

Click to expand...

Thanks for your reply.
But these kind of theory (i.e. some current or less voltage) is available in any school book.

Actually I am looking for some mathematical explanation. That will help me to analyze this circuit better. That means before simulation, I should know where the voltage is going to settle by changing R or C value.

Can you suggest me any book or link for these kind of stuff?

Thanks in anticipation.

If you simply charge the clock frequency you will see some different waveforms which might help you to understand why you only get 2.5V at a high frequency.



Keith.