Hey david,
Max fanout load of net is max number of loads the net can drive. DC attempts to ensure that the sum of fanout_load attr for input pins on nets driven by specified ports or nets in the design is less than given value set in set_max_fanout command.
Fanout load value is unit less and its numerical contricution to total fanout load. we will see one example how DC works on this..
Lets say in your design, two inverters in your design ( TSMC_INV1_A1 and TSMC_INV1_A25). fanout_load attr can be found for these by using below commands.
get_attr your_lib/TSMC_INV1_A1 fanout_load
get_attr your_lib/TSMC_INV1_A25 fanout_load
assume these commands returns 0.25 and 3 resp. if you have following in your script, set_max_fanout 6 [get_ports IN1].
DC can load port IN1 with 6/0.25 = 24 TSMC_INV1_A1 cells and 6/3 =2 TSMC_INV1_A25 cells.
Find out the default_fanout_load of library using get_attr your_lib default_fanout_load. Its gives whats the value of your lib setting.
Second choice is, we usually put the restriction as 20 and synopsys recomends till 50 for data paths and ideal for clock and reset paths.
Third choice is, use the graph to find out your design stastics. report_net_fanout -threshold <your threshold value> . Collect the data and analyze , does DC optimizing or where do you need more fanout synthesis and then put realistic value to your design or partiular module.
Best of luck..
Regards,
Sam