about RZ in CT sigma-delta

I am designing CT sigma-delta. and using RZ (return to zero) feedback. So, is RZ really return to zero (common mode voltage), which is in regardless of the input signal, during half of the clock, or it is return to the voltage, which equals the input voltage at that time, so, half of the clock, the integrator does not do the integration?

Since I found that if return to exact zero, with the input voltage swing, the integrator would do the wrong interation.

You should return feedback signal to common-mode voltage during RZ time.
The intention is that the integrator is not intergating the feedback signal in RZ time. However, it might continue to integrate input signal, depending on your particular SD modulator implementation and spec.

steer said:

You should return feedback signal to common-mode voltage during RZ time.
The intention is that the integrator is not intergating the feedback signal in RZ time. However, it might continue to integrate input signal, depending on your particular SD modulator implementation and spec.

Click to expand...

if so, the output signal would have bigger swing than input signal, because at every half clock cycle, integrator do the signal integration without feedback. I think it is not the good mapping of the input signal, am I right?

jiaming_lee said:

steer said:

You should return feedback signal to common-mode voltage during RZ time.
The intention is that the integrator is not intergating the feedback signal in RZ time. However, it might continue to integrate input signal, depending on your particular SD modulator implementation and spec.

Click to expand...

if so, the output signal would have bigger swing than input signal, because at every half clock cycle, integrator do the signal integration without feedback. I think it is not the good mapping of the input signal, am I right?

Click to expand...

NRZ and RZ do not share the same transfer function, and for RZ to achieve the same swing as NRZ, you need to scale the coefficients; refer to richard's recent book page 266-270, it's called dynamic scaling.

the maximum integrator output can be controlled and it can be scaled to any value, but the trade-off is the capacitor size might be very large, or impractical. so the integrator output swing is not an issue in system simulation.