about resize functions

i want to ask you whether resize function is supported in xilinx if yes can you give an example for the same in vhdl using xilinx software?

yes it is. All the resize function does is add/remove bits to a bus. This is essentially free in terms of logic. resize is really a code formality.

TrickyDicky said:

yes it is. All the resize function does is add/remove bits to a bus. This is essentially free in terms of logic. resize is really a code formality.

Click to expand...

this is the vhdl code i have written in xilinx software
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

use IEEE.numeric_std.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity project1 is
port(a:in STD_LOGIC_vector(23 downto 0);
b:in STD_LOGIC_vector(23 downto 0);
zut STD_LOGIC_vector(24 downto 0));
end project1;

architecture Behavioral of project1 is

begin

z<= (resize(a,25))+(resize(b,25));



end Behavioral;

the error i got is

ERROR:HDLParsers:808 - "D:/projects final/signextension/project1.vhd" Line 43. resize can not have such operands in this context.
ERROR:HDLParsers:808 - "D:/projects final/signextension/project1.vhd" Line 43. resize can not have such operands in this context.

Process "Check Syntax" failed

can you rectify the problem?

yes. First of all delete the std_logic_arith and std_logic_unsigned libraries - they are non-standard VHDL libraries. Also, std_logic_arith conflicts with numeric_std, hence another reason to delete it.

finally, you cannot resize a std_logic_vector. You need to resize a signed or unsigned type. so you need to cast a and b to one of these types.

assuming you need signed, you need to write:

z <= resize( signed(a), 25) + resize( signed(b), 25);

TrickyDicky said:

yes. First of all delete the std_logic_arith and std_logic_unsigned libraries - they are non-standard VHDL libraries. Also, std_logic_arith conflicts with numeric_std, hence another reason to delete it.

finally, you cannot resize a std_logic_vector. You need to resize a signed or unsigned type. so you need to cast a and b to one of these types.

assuming you need signed, you need to write:

z <= resize( signed(a), 25) + resize( signed(b), 25);

Click to expand...

The problem is i am using this resize function for the zero latency cic interpolation filter vhdl code where the bit growth is happening at the comb
and the integrator sections of the zero latency interpolation filter.In my code i am using the input to the zero latency cic interpolation filter to be std_logic_vector and for cic filter i have to compulsary use signed as per your reply.so can you tell me to convert the std_logic_vector to signd and again finally the added answer at the output of the last integrator stage which is signed to again std_logic_vector?Is it possible in vhdl code written in xilinx software for conversion between std_logic_vector to signed and again vice versa?Can you explain me this conversion with vhdl code written in xilinx software?

kannan2590 said:

Is it possible in vhdl code written in xilinx software for conversion between std_logic_vector to signed and again vice versa?Can you explain me this conversion with vhdl code written in xilinx software?

Click to expand...

You were already given the code, the conversion is the 'signed()' function call. To elaborate a bit, let's say you have the following signals:
signal a: std_logic_vector(7 downto 0);
signal b: signed(7 downto 0);

Then you can convert from one type to the other like this...
a <= std_logic_vector(b); -- Convert 'b' to a std_logic_vector
b <= signed(a); -- Convert 'a' to a signed

Although I'm using the word 'convert', you can also validly think of it as 'interpret'. In other words, interpret the std_logic_vector as being a signed numeric thing. However you want to view it doesn't matter. The main point is that VHDL is a strongly typed language so you can't assign something of type 'abc' to something else that is of type 'xyz', there must be a conversion function. Generally speaking (and definitely in the case of signed/unsigned/std_logic_vector conversions), there is no logic that gets synthesized here by using this function.

The earlier post showed how you can do the conversion of the inputs into signed values, add them, and convert the result back to a std_logic_vector. You might look at that and say that's a lot of type conversions (and typing) and start to curse VHDL strong typing. That would be the wrong approach. If you find yourself doing lots of type conversions, what it typically means is that the signals are being defined as the wrong type in the first place. The proper solution would be to define the signals to be the correct type. In your example, a, b, and z should have all been defined as type signed. You simply need to replace 'std_logic_vector' with 'signed' in the entity and move on. Now your addition becomes

z <= a + b;

Now doesn't that express your design intent most clearly? No type conversions are needed because the signals are defined to be the right type. You have much less typing to do and much clearer code because there are no type conversion functions cluttering up the code...not only that but the word 'signed' is shorter than 'std_logic_vector'.

Kevin Jennings