About random data generation using verilog language

[sycolegend]

Hi all,

My design needs a huge number of random data. I have used $random to generate random data. But these data is all the same when I restart the simulation. Can any body telll me how to generate pure random data in verilog.

Thx in advance

 

[wylee]

If you are using Cadence, there is a cell called "rand_bit_stream" inside the library name "ahdlLib". You can use that to generate random data.

If you are not talking about Cadence, maybe the follow code might help you

integer iseed;
bit = abs($random(iseed)) & 1;

hope this helps!

 

[sakthi_tallika]

If you want different seed need to be used, please try this.

reg [31:0] data ;
initial
data = $random();

<your loop>
data = $random(data) ;

this logic will change your seed for each iteration.

regards,
sakthi.

 

[sycolegend]

Thx