about rail to rail problem

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samuel

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hello, every one.

I had designed a rail to rail operational amplifier. however, when I use this operational amplifier, some problems happens as follows.

when a stable voltage level(3V) is applied to positive input terminal of OPA, and another stable voltage level (2.999V) is applied to negtive input termnal of OPA. the output voltage is varying with about 50mv. why? the circuit is attached.
 

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it is maybe that the PSSR of OPA is too low? or it is maybe that the Vos of OPA is too large?
 

Are you reporting a simulation? If so which analysis type, settings? Power supply?

What do you mean with "the output voltage is varying"? Static deviation, noise?
 
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    samuel

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FvM said:
Are you reporting a simulation? If so which analysis type, settings? Power supply?

What do you mean with "the output voltage is varying"? Static deviation, noise?
Click to expand...

ok now, I had tapeout this OPA. when I apply this OPA to the practical cirucit, some problems happen as above.

"the output voltage voltage is varying" means that , if the output voltage should be 2.7V, but it varies about 2.7V+/-50mV stochasticly.
 

The voltage difference is only 1 mV. This will correspond to a current of 1 uA through the resistors. This will no doubt result a very unstable solution. Making the voltage difference larger and the resistors smaller will solve the issue.
 

ejeet said:
The voltage difference is only 1 mV. This will correspond to a current of 1 uA through the resistors. This will no doubt result a very unstable solution. Making the voltage difference larger and the resistors smaller will solve the issue.
Click to expand...

thanks for your reply.

why?
but if I apply another OPA(buy in the market) to this inverting amplified circuit, this unstable phenomena will not appear.
 

it varies about 2.7V+/-50mV stochasticly
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I understand, that you are not discussing a static offset voltage or slow drift? In this case, you should review the input noise voltage and particularly flicker noise specification of your design. 100 uVpp noise voltage actually seems to be far above usual bounds. It can indicate either a design fault or a process problem.
 

ok, now, I understand your opinion that input noise cause output variations.

Is it possible that low PSRR spec cause this phenomena？that is to say, power supply noise cause this variations.
 

It's possible of course. As another question, are you sure, that no output or input stage is in saturation?
 

FvM said:
As another question, are you sure, that no output or input stage is in saturation?
Click to expand...

what means? If output stage or input stage is not saturation, can it causes output variations? why?

thanks.
 

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