About process corner lot

[asicgiga]

When developing new semiconductors, corner lots are sometimes performed.

However, just as the process of the TT target forms a spread containing SS, TT, FS, SF,
the corner lot will also form a new spread that is not in the process library. (outer range from process model library)

Then, it is expected that chips from corner lot are differ from the process model used during design, and it will be uncertain whether they will operate.

Can you explain in detail the analysis process performed through corner lot?

And another question, is it possible to mass produce it as a shifted process? (e.g. shifting to FF is helpful for timing margin)

 

[glennramalho]

Hi, I am having trouble understanding your question. Yes, like you said, first, the process engineers plan on what they want, then they can use a number of tools to try to simulate and predict how the process is going to be. After that they produce a test chip that is measured for each corner. Depending on the process node that this can include different issues, like optical problems, temperature ranges, derates, and so on. Like you said, this is why we wind up with some chips comming out slightly faster, some much faster, some with say the Pmos much stronger, some with it weaker, and so on. This gives us the corners. So we aim for the typical but get everything.

The next task then the wafers are tested to make actual statistics, the corners of what is acceptable are defined. I remember several years ago seeing the device physics guys going to the lab and measuring each transistor by hand, blowing each resistor, and so on to see the limits. Today it might be more automatic, this was 20 years ago.

Once all this is done the data is fed to the tools. Of course, if it is not satisfactory, one can always tweak the process, and there are often some rounds of that before the process is ready to be used. So the early preliminary PDK can be quite different from the final PDK details sent to the customer. Sometimes customers are too in a hurry to get something out and then there is already a product on these preliminary runs but then the designer often puts in lots of margin to account for changes.

Now, what do you mean? To shift the process towards the FF, think about that. This would mean the transistors need to switch faster. So, yes, one could design a variant process where some parameters were tweaked, so one could perhaps change the K. These variant processes do exist sometimes. This takes time though and you would probably just define a new typical and then shift everything. Another thing that happens is sometimes your library provider will design libraries with different VTs to get a faster library at cost of more energy and a slower more power friendly library.

Is this whay you mean? Or do you mean perhaps making processes that use extreeme temperatures. They do exist too but usually only few foundries focust on them, for example chips that are expected to operate above 100C. But the whole process is quite odd in this case.

 

[dick_freebird]

The fab rats know how to bend the shot to get short L thin Tox low VT or whatever. Somebody does the DoX and they execute. Your over-calendar-time-and-oopsie-plus-sandbag "corners" are way way wider than a single lot's scatter.

 

[asicgiga]

Hi, I am having trouble understanding your question. Yes, like you said, first, the process engineers plan on what they want, then they can use a number of tools to try to simulate and predict how the process is going to be. After that they produce a test chip that is measured for each corner. Depending on the process node that this can include different issues, like optical problems, temperature ranges, derates, and so on. Like you said, this is why we wind up with some chips comming out slightly faster, some much faster, some with say the Pmos much stronger, some with it weaker, and so on. This gives us the corners. So we aim for the typical but get everything.

The next task then the wafers are tested to make actual statistics, the corners of what is acceptable are defined. I remember several years ago seeing the device physics guys going to the lab and measuring each transistor by hand, blowing each resistor, and so on to see the limits. Today it might be more automatic, this was 20 years ago.

Once all this is done the data is fed to the tools. Of course, if it is not satisfactory, one can always tweak the process, and there are often some rounds of that before the process is ready to be used. So the early preliminary PDK can be quite different from the final PDK details sent to the customer. Sometimes customers are too in a hurry to get something out and then there is already a product on these preliminary runs but then the designer often puts in lots of margin to account for changes.

Now, what do you mean? To shift the process towards the FF, think about that. This would mean the transistors need to switch faster. So, yes, one could design a variant process where some parameters were tweaked, so one could perhaps change the K. These variant processes do exist sometimes. This takes time though and you would probably just define a new typical and then shift everything. Another thing that happens is sometimes your library provider will design libraries with different VTs to get a faster library at cost of more energy and a slower more power friendly library.

Is this whay you mean? Or do you mean perhaps making processes that use extreeme temperatures. They do exist too but usually only few foundries focust on them, for example chips that are expected to operate above 100C. But the whole process is quite odd in this case.

Thank you for your kind reply.

I understand that the process setup requires a lot of repetition and experimentation.

My question was about corner lot for new semiconductor products produced in mature process. (not for new process development)
There will be many IC samples outside the library corner with corner lots (Much more than TT),
and my question was, what is the process for testing those IC samples. (e.g Electrical characteristic test in EDS & F/T)

About the mass production with shifted process, I understood your reply.

 

[ThisIsNotSam]

I still don't understand the question. You can think of SS as a contract between you and the foundry. You should not be getting any chips that perform worse than SS in a mature process. Anything near TT, near FF, or above FF, is icing on the cake. I don't see an immediate need for testing or additional scrutiny of chips that perform better than SS.

 

[dick_freebird]

Check your starting assumption, that your new product lot will receive any processing outside the mature process production envelope. Aside from a fluke (or a real sloppy fab choice) the odds are 3- or 4-sigma low. Probably more like 3 in the fab and 4 in the PDK.