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Normally, Probe pads will be added in layout by layout designers but defined / specified by circuit designer. The design rules will be specified in foundries process design kit.
The probing will be done by probe cards automatically or manuallu by using probe pins.
Does the probe pad opening dependant on the probe pitch size used. As for example a GS/SG probe requires a probe opening around 150um due to the probe pitch size. Kindly do feedback on this. Thank You
Pads for external bonding = Usually supplied by the fab. Different for digital, analog, buffer, and also come with a full complement of ESD devices. (depending on your subscription)
Pads for probing = Usually done in-house and are determined by the design of the probe used to test. If the probe spacing is 150um and there are 3 probes, your layout should be exactly similar. Specs to be found in manuals that came with your probes.
Hi,guys!
I'm reading "cmos IC layout"
It's said " Probe pads ,are used exculsively for the preproduction debugging and
evaluation stage.Product engineers use probe pads to check the functionality and
timing of internal nodes of that have not been qualified for production.
Probe pads can be placed anywhere on the die ,since they are used when the die
is completely unprotected. The size of the probe pads is dependent on the equipment that is used.
Historically,probe pads were not explicitly implemented,because a single via was big enough for the probes that were avialable .As layer geometries have shrunk,a single via has become too small for physical probing.Generally ,a probe pad that is in the range of 1 um*um is sufficient. Page 205.
Usually,the probe pad is added at where that the design parameter is controlled by designer. In other words, the designer need to monitor which parameter,and a probe pad is added at the position of the parameter's out .
the size of probe pad and the space between the probe pad are specified by process foundry.
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