About post-simulation issue

[flyer]

Hi,
Now I meet a post-simulation issue. My RTL code is verilog code. After per-simulation, I did synthesis by using Design Complier and did place and route by using encounter. When I did place and route, I fixed some hold violations by using optimization of encounter. Then, no setup, hold, max_capacitance, max_transition and max_fanout violations. But the function is different from the functional simulation(per-simulation) when I did post-simulation by using NClaunch. Why? Thanks.

 

[ebuddy]

2 possible reasons: 1. netlist changes you did when fixing timing actually change the function. You can find it out if this is the case by running logic equivalence check. 2. the gate-level sims has "x" where you RTL does not. "x" may mess up your sims.

 

[flyer]

2 possible reasons: 1. netlist changes you did when fixing timing actually change the function. You can find it out if this is the case by running logic equivalence check. 2. the gate-level sims has "x" where you RTL does not. "x" may mess up your sims.

Thanks for your answer. The netlist simulation after place and route has no "x", but the functions are some changes compared to functional simulation. "1. netlist changes you did when fixing timing actually change the function. You can find it out if this is the case by running logic equivalence check. " There is no timing violation in Encounter, so how to find and fix the timing? Thanks a lot.

 

[ebuddy]

When the timing gets fixed, Encounter tool modifies the netlist (inserting buffers, re-structure the logic, etc). To make sure that the modified netlist has the same functionality as the original netlist, we usually run LEC (logic equivalence check). There are tools available specifically for this (like Conformal from Cadence, etc).

Have you run the gate-level sim using the netlist after the synthesis (before the layout)? If that netlist gives you the right result, then you can be sure that it is the Encounter that causes the problem. If not, then the problem exists in synthesis stage. Either way, the LEC will help you in your debugging effort.

 

[flyer]

When the timing gets fixed, Encounter tool modifies the netlist (inserting buffers, re-structure the logic, etc). To make sure that the modified netlist has the same functionality as the original netlist, we usually run LEC (logic equivalence check). There are tools available specifically for this (like Conformal from Cadence, etc).

Have you run the gate-level sim using the netlist after the synthesis (before the layout)? If that netlist gives you the right result, then you can be sure that it is the Encounter that causes the problem. If not, then the problem exists in synthesis stage. Either way, the LEC will help you in your debugging effort.

I don't run gate-level simulation using the netlist after synthesis. I'll try. By the way, there are two chips in my design, so I do synthesis and place and route respectively. For postlayout simulation, I just add two sdf files in the testbench like this:
initial
begin
$sdf_annotate('"***/top1_min.sdf",tb_top.top1);
end
initial
begin
$sdf_annotate('"***/top2_min.sdf",tb_top.top2);
end
Is it right?Thanks.