analogman
Junior Member level 1
resolution of pipeline A/D converter is limited by capacitor mismatch.
if consider that 1bit mdac(cap number=2) used in pipeline, cap mismatch=0.1% means
a normarilized cap value is 1.0, and the other is 1.001.
but if consider that 2bit mdac(cap number=4) used in pipeline. if cap mismatch= 0.1%,
how should I set up respective cap values?
thanks
if consider that 1bit mdac(cap number=2) used in pipeline, cap mismatch=0.1% means
a normarilized cap value is 1.0, and the other is 1.001.
but if consider that 2bit mdac(cap number=4) used in pipeline. if cap mismatch= 0.1%,
how should I set up respective cap values?
thanks