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about pipeline a/d converter

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analogman

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resolution of pipeline A/D converter is limited by capacitor mismatch.

if consider that 1bit mdac(cap number=2) used in pipeline, cap mismatch=0.1% means
a normarilized cap value is 1.0, and the other is 1.001.

but if consider that 2bit mdac(cap number=4) used in pipeline. if cap mismatch= 0.1%,
how should I set up respective cap values?

thanks
 

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