About parasitic resistance calculation

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yxo

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VirtuosoXL and ASSURA are used. How equivalent extracted resistance is calculated at MOS gates? Which ponts are involved in calculation? Some times I think that it is lie %)
 

In addition to parasitic extraction also MOS devices are extracted. In all extraction tools I know you cannot extract parasitics above a "device recognition area". A MOS devise is recognized by poly over LOCOS. So the parasitic resistance of poly is only to the edge of the MOS. The distributed resistance of the MOS poly gate is in cooperated into newer MOS models. Thats the way its works.
 

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