about non-overlap clock circuit

[lhlbluesky]

in many sc ciruit, two-phase non-overlap clock is usually used. here, i have some questions:

1, make a 1M clock for example (Fclk=1M), what is the time interval of non-overlap (Tnon-overlap)? what is the percentage of Tnon-overlap in Tclk (1us)?
or what is the minimum value of Tnon-overlap? how to decide the time interval of non-overlap (Tnon-overlap) for a given Tclk?

2, to realize bottom plate sampling, phi1 is usually used (phi1d and phi2d are two-phase non-overlap clock), phi1 and phi1d have almost the same rising edge, but phi1 has a earlier falling edge than phi1d (interval = Tearly). here, what is the value of Tearly? what is the percentage of Tearly in Tclk (1us)? how to decide the value of Tearly for a given Tclk?

i need some explanations, oe some related papers.
thanks all for your reply. thanks.

 

[karesz]

Hi,
I think-this is depend on your application, but I will guess for 5-10%...
Goal is of nonoverlapping: your switch 1 must be full on/off befor switch2 is to change in off/on...
K.

 

[dick_freebird]

You typically see CMOS timings specified 50%-50%, but what
you are after is to eliminate any significant switch cross-
conduction. So you might want to be criticizing design
simulations against something like 95%-5% (you should
assign timing thresholds to a voltage where worst case FET
conduction is below your level of concern). That is, at the
worst case corner you want the prior phase fully settled
(or nearly so) to its destination rail before the next begins
to lift off.

Probably look at your worst case subthreshold slope, high
temp, max supply and worst common mode point for FET
leakage.

If you are using the simulator to pick values you can loop
it wide and pick off the point where more dead time ceases
to improve accuracy, working backward from "that ain't right".