lhlbluesky
Banned
low power design and pipelining
i want to design a pipelined adc which is low power,
the resolution is 10bits,then
can anyone tell me how to decide the resolution of every stage,
someone tell me the 2.5 bit per stage is the best power-optimized,is that right?
can anyone give me some advice?
besides,for low power design ,what considerations should i take?
please help me.
any advice or related papers are expected,thanks first!
i want to design a pipelined adc which is low power,
the resolution is 10bits,then
can anyone tell me how to decide the resolution of every stage,
someone tell me the 2.5 bit per stage is the best power-optimized,is that right?
can anyone give me some advice?
besides,for low power design ,what considerations should i take?
please help me.
any advice or related papers are expected,thanks first!