Oxide thickness is not controllable in the real sense of the word. It changes with temperature and fabrication conditions. It varies from transistor to transistor depending on the doping profile during the fabrication.
There is a typical, slow and a fast corner for it. A good design should take this process variability into account. VCOs for instance, can be off by as much as 2x in frequency as a result of such variation.
During layout, you just use the DRC rules as pointed out right above this post.