surerdra
Junior Member level 1
- Joined
- Feb 15, 2014
- Messages
- 18
- Helped
- 1
- Reputation
- 2
- Reaction score
- 1
- Trophy points
- 3
- Activity points
- 237
i implemented vhdl program for one of the digital design, here latch (using nor gates) is one of the components, while i simulate the output of latch is
undefined--u--, if i plase some delay(after x ns) in inputs of latch the out put is came, but the hardware didn't consider this type(after x ns) of commands.
if i check that latch component individually the out put came with out any delay at inputs, but while i using that component in my program the output not came with out delay, i add some dalay using buffrs also but i didnt get, what i do?
undefined--u--, if i plase some delay(after x ns) in inputs of latch the out put is came, but the hardware didn't consider this type(after x ns) of commands.
if i check that latch component individually the out put came with out any delay at inputs, but while i using that component in my program the output not came with out delay, i add some dalay using buffrs also but i didnt get, what i do?