About IN-OUT ports in verilog

Similar threads

• I

  1st order sigma delta output is wrong verilog Cadence

  • Started by InvokeMeWell
  • Nov 10, 2024
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• R

  [Moved]Verilog issue with output even though condition is met(dice game)

  • Started by ralph_verilog
  • Oct 21, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] Delaying the output by 2 clock cycles in FSM in VHDL

  • Started by metamisers
  • Aug 2, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  How do I assign decimal values in verilog?

  • Started by mahesh_namboodiri
  • Jan 31, 2024
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• E

  Which simulator should I use for verilog?

  • Started by electronicslab
  • Oct 26, 2024
  • Replies: 9

  PLD, SPLD, GAL, CPLD, FPGA Design