about i2c implementation in verilog

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anoop12

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Hi,

For I2C, both scl and sda are bi-directional.
For the RTL of i2c master, is it advisible to declare sda as "inout" or as separate ports as "sda_in", "sda_out" and "sda_output_en".

Is this to avoid use of tri state buffer on SoC as they are dificult for timing analysis?

Thanks
 

In some design enviroments, you possibly want to implement the output buffers as explicite low-level primitive. This is supported by the separate signals.
 

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