littlej_zju
Member level 2
ocv hold margin
In timing signoff condition, there is ocv+100ps hold margin for hold time check.
Where does the "100ps" come from?
Is it related with design speed? (For 400Mhz or 800Mhz design, do they use the same hold margin?)
In timing signoff condition, there is ocv+100ps hold margin for hold time check.
Where does the "100ps" come from?
Is it related with design speed? (For 400Mhz or 800Mhz design, do they use the same hold margin?)