aspirinnnnn
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I have a generate block in SV like the following:
it seems that vcs cann't recognize condition expression in the ports, is there anyway i can work around this？or i have to do it by hand8-O
Code:
genvar i;
genvar j;
generate
for (i=0;i<8;i++)
for(j=0;j<8;j++) begin:peBlockGen
peLogic U_peLogic(
.clock(clock),
.reset_n(reset_n),
.inst(inst),
.din_self(din_self[i*8+j]),
.din_up ( i==0 ? din_up[i] : din_self[(i-1)*8+j] ),
.din_right( j==7 ? din_right[i] : din_self[i*8+j+1] ),
.din_down ( i==7 ? din_down[j] : din_self[(i+1)*8+j] ),
.din_left ( j==0 ? din_left[i*8+1] : din_self[i*8+j-1] ),
.imageinport(j==0 ? imageinport[j] : imageport[i][j-1]),
.imageoutport(j==7? imageoutport[j] : imageport[i][j]),
.alu_result(alu_result[i*8+j])
);
end
endgenerateit seems that vcs cann't recognize condition expression in the ports, is there anyway i can work around this？or i have to do it by hand8-O