About EMI solution at chip layout stage and board/system

Status
Not open for further replies.
R

risccpu

Junior Member level 2
Joined
Oct 21, 2005
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,421
Hi,

Could you please tell me how to reduce noise and/or EMI in the chip layout stage? And how to reduce noise from SOC device to board/system? What are the related EDA tools?

Thanks a lot.

Best Regards,
risccpu
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…