libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_SIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity subfilt1 isPort( dout :outSTD_LOGIC_vector(27downto0);
clk :inSTD_LOGIC;
reset :inSTD_LOGIC;
din :inSTD_LOGIC_vector(7downto0));end subfilt1;architecture Behavioral of subfilt1 iscomponent DFF isport(
q :outSTD_LOGIC_vector(7downto0);--output connected to the adder
Clk :instd_logic;-- Clock input
rst :instd_logic;
d :inSTD_LOGIC_vector(7downto0)-- Data input from the MCM block.);endcomponent;signal H01,H049 :STD_LOGIC_vector(19downto0):=(others=> '0');signal MCM02,MCM03 :STD_LOGIC_vector(27downto0):=(others=> '0');signal add_out02 :STD_LOGIC_vector(27downto0):=(others=> '0');signal Q02 :STD_LOGIC_vector(27downto0):=(others=> '0');signal din1:std_logic_vector(7downto0):=(others=>'0');begin
H01 <="11111111111111110101";
H049 <="00000010100101011100";--dff2 : DFF port map(Q02,Clk,MCM02);
dff2 : DFF portmap(q => din1,Clk=>clk,rst => reset,d => din);
p01001:process(Clk,reset)beginif reset='0' then
dout <="0000000000000000000000000000";elsif clk'eventand clk='1' then
MCM02 <= din*H01;
MCM03 <= din1*H049;
add_out02 <= MCM02+ MCM03;
dout <= add_out02;endif;endprocess p01001;end Behavioral;
when i synthesize this code i get warning messages like <dout 1>,<dout 2>,<dout 3>,<dout 4>,<dout 5>,<dout 25>,<dout 26>,are unconnected.so i am using vertex 4 fpga and the simulation results are coming correct inspite of these warning messages . whether these warning messages effect the output in fpga and if it effects how to correct and solve such warning messages?