about DC synthesis, set_max_delay

below is a graph from "Advanced ASIC chip syntheis using synopsis ....", I can not understand it, can any one explain for it a bit. thanks in advance.

Although, Synopsys recommends defining only a single clock per block, there are situations where a block may contain multiple clocks, each with a different frequency. To constrain such a block, one may
define all the clocks in the block using the normal create_clock and set_dont_touch_network commands. However, it becomes tedious to assign input delays of signals related to individual clocks. To avoid this situation, an alternative approach is to define the first clock (the most stringent one) using the normal approach, while constraining other clocks through the set_max_delay command, as shown below.

dc_shell -t> set_max_delay 0 –from CK2 –to [all_registers –clock_pins]

The value of 0 signifies that a zero delay value is desired, between the input port CK2, and the input clock pins of all the flops within the block. In addition, one may also need to apply the set_dont_touch_network for other clocks. This method is suitable for designs containing gated clocks or resets.


My question is that : since there are several asynchronous clocks in that block, so why all the registers are set_max_delay 0 relative to one of the clock.

for example, if I have the following verilog code, could you give a example to set_max_delay
// here I try to synchronize data between clk domain 1 and domain 2, even though data can be synchronized more than one time or some data can be skipped, we don;t care it now.//
module test(
input clk1,rst1_n,
input clk2,rst2_n,
input data_from_clk1,data_from_clk2,
output reg data_to_clk2,data_to_clk1
);

reg data_1clk_delay_to_clk1, data_1clk_delay_to_clk2;

always @(posedge clk1 or negedge rst1_n)
if (!rst1_n)
{data_to_clk1,data_1clk_delay_to_clk1} <= 0;
else
{data_to_clk1,data_1clk_delay_to_clk1} <= {data_1clk_delay_to_clk1,data_from_clk2};

always @(posedge clk2 or negedge rst2_n)
if (!rst2_n)
{data_to_clk2,data_1clk_delay_to_clk2} <= 0;
else
{data_to_clk2,data_1clk_delay_to_clk2} <= {data_1clk_delay_to_clk2,data_from_clk1};

endmodule

So, in this case, how should I use set_max_delay?

a longgggggggg.... post:shock: