about CMOS wild wing current mirror error

[andy2000a]

Hi
I design a wild swing current mirror ..
(CMOS Circui design & layout & simulation page 456 fig-20.27 )
but this current have large error , from papaer , I know mismatch
in CMOS current mirror , should ne include Vt , Lamda effect ...
but usuall 1% error , but my real chip is large than 3% ..
I don't why ?? layout problem ??

some ref peper
on attach file

 

[andy2000a]

another paper

 

[andy2000a]

another

 

[Humungus]

Layout is the most likely cause.

Also take into account transistor sizes. Remember that all "deltas" are divided by sqrt(W.L) So, to reduce the standard deviation of each component (Id and Vt) you must increase transistors sizes. Another point in which ALL TRADITIONAL BOOKS make a mistake is about the term (Vg-Vt) that divides delta Vt. Actually you should multiply delta Vt by gm/Id. What they say is that as Vg-Vt increases (gm/Id decreases), mirror matching is improved.

This is completely FALSE. As you normally have Id as a design constraint, increasing gm/Id enlarges transistor size so that matching is actually improved.

I hope you have got the point.

We'll keep in touch.

 

[andy2000a]

Hi

as I know some Book said

Io/Ii = (1 + Lamda*Vds2) / (1+ Lamda*Vds1)
= 1 + .... - 2* deltaVt / (Vgs-Vt)
(I upload model.rar paper said this Equation ..)

your said should be change to
-2 * deltaVt *(Vgs-Vt ) ??



or you can give me paper ..
thank you

 

[Humungus]

deltaVt= sigmaVt/sqrt(W.L)

sigmaVt is a constant (at a given temeprature) given by the fab and depends on process (etching, device type etc)

On the other hand, the term 2.deltaVt/(Vgs-Vt) should indeed be (make the equations on your side)
gm.deltaVt/Id = gm.sigmaVt/(Id.sqrt(W.L))

Consider that gm=dId/dVgs, so dId/dVt=-gm. Then
dId/Id=-gmdVt/Id

Up to you to continue.

For a fixed L (determines max operating freq) and fixed Id (you design for a fixed current), gm/((Id.sqrt(W.L)) increases as Vgs-Vt increases. All books make a mistake here. Go to spice, choose a model that describes the transistor behavior in a continuous way (EKV for instance) and plot gm/((Id.sqrt(W.L)) for a fixed L and ID (you must change W).

Don't believe books without thinking by yourself. All traditional books were developed in base to the equation
Id=0.5.µ.Cox.(W/L)(Vgs-Vt)^2

This equation is only valid in strong invertion. Take a look at the book of Tsividis on MOS modeling to see what I'm talking about.

You must also know that terms depending on "sigmas" mean random mismatch. On the other hand, temrs including "lamdas" mean systematic mismatch. Do you have access to Sansen's book on analog design? It is just to see what it is random and what systematic. This book also makes the mistake deltaVt/(Vg-Vt). Terms depending on lamdas can be reduced by using cascodes so that Vds of both transistors in a current mirror are equal. Then, no current error due to non equivalent bias conditions.

Developing the equations may be tedious but, believe me, you'll impress your advisor.

Tell me if you need further help.

 

[andy2000a]

deltaVt= sigmaVt/sqrt(W.L)

sigmaVt is a constant (at a given temeprature) given by the fab and depends on process (etching, device type etc)

On the other hand, the term 2.deltaVt/(Vgs-Vt) should indeed be (make the equations on your side)
gm.deltaVt/Id = gm.sigmaVt/(Id.sqrt(W.L))

Consider that gm=dId/dVgs, so dId/dVt=-gm. Then
dId/Id=-gmdVt/Id

Up to you to continue.

For a fixed L (determines max operating freq) and fixed Id (you design for a fixed current), gm/((Id.sqrt(W.L)) increases as Vgs-Vt increases. All books make a mistake here. Go to spice, choose a model that describes the transistor behavior in a continuous way (EKV for instance) and plot gm/((Id.sqrt(W.L)) for a fixed L and ID (you must change W).

Don't believe books without thinking by yourself. All traditional books were developed in base to the equation
Id=0.5.µ.Cox.(W/L)(Vgs-Vt)^2

This equation is only valid in strong invertion. Take a look at the book of Tsividis on MOS modeling to see what I'm talking about.

You must also know that terms depending on "sigmas" mean random mismatch. On the other hand, temrs including "lamdas" mean systematic mismatch. Do you have access to Sansen's book on analog design? It is just to see what it is random and what systematic. This book also makes the mistake deltaVt/(Vg-Vt). Terms depending on lamdas can be reduced by using cascodes so that Vds of both transistors in a current mirror are equal. Then, no current error due to non equivalent bias conditions.

Developing the equations may be tedious but, believe me, you'll impress your advisor.

Tell me if you need further help.

thank you very much ...

 

[electronrancher]

it could be several things - i would search for one of these.
-minimum size devices used for precision matching

-matched mirrors layout far from each other

-using very low currents, so device is falling into triode

-mismatched output impedance (reference mirror feeds into 100kOhm, but test mirror goes to a pin that you measure using 10kOhm - Rout of device again related to first few suggestions

-different signal paths (first mirror handed off through 2 nmos/pmos pairs, second handed off through 4)

any of that may be the suspect? if it is mismatch on a small project die, i think these have bigger effect than diffusion gradients or masking errors on such a small die. (well, unless one has gate horizontal and the other has gate vertical) second tier effects would be temp gradients if you use a power device, and third tier effects would bring process variation into effect. for most part, i see process variation cause trend across the surface of a wafer to 3%, not within a single die to 3%.