about CMOS buffer design

[marlboro_x]

cmos buffer

how to design a cmos buffer using simply inverters.Are there any rules to size the MOS-FET?
can anybody guide me to some materials about this topic.
Thx in advance.

 

[avinash]

cmos buffer design

depending upon the load ,o/p rise and fall time requirement and delay requirement of buffer,you can design your buffer.

 

[opamp741]

cmos buffer

look for the material on "logical effort"..That will help u for sure..

 

[andy2000a]

buffer using cmos

what type buffer ?? logic invert buffer ? or volt buffer
??

if you means CMOS invert buffer , if your load is very large , use Tap buffer --> see CMOS analog circuit design layout & sim by Baker

we usually min Length for cmos logic , but if your buffer driver to I/O pad should consider ESD .

 

[marlboro_x]

how to design a super buffer

i want to use several cmos inverters to increase its driver ability,to drive more current.
Any useful material?
Tks a lot.


reguards.
marlboro_x

 

[nitu]

super buffer design

You can refer to the Digital Integrated Circuits by Rabaey and Logical Effort by David Harris.

 

[pixel]

buffer design cmos

There is some optimal W/L ratio, for minimal delay, that shows how much next CMOS inverter stage has to be greater then previous...
(As I remember next stage should be e=2.71 times bigger than previous.)

In this book you can find more about this , and optimal inverters number.

Application Specific Integrated Circuits, pages 138-141

 

[chinito]

design of cmos buffer

I think what you're refering to goes by the name of 'super buffer'. It's nothing more than series of interters starting to minimum size to larger sizes as you move from right to left towards your load. You don't design a big inverter because that'll offer too much load to the your previous logic. Super buffer simply distributes the load in many stages. Nothing new, same old time eqns apply for each stage.

 

[dumbfrog]

logical effort + stage ratio + buffer

rule of thumb => 3/1 for p/n mos and 1:3 drive for previous stage to the next

 

[marlboro_x]

i/o buffer+cmos logic

pixel:

It's true that the W/L of next stage should be 2.72times the former.But I found the book u guided is talking about ASIC,and i haven't so much points to d/l.Is there any material smaller ?

dumbfrog:

U R absolutely right.I've read some paper saying the next stage Load Capcitor should be about 3times the former.But how can i see the value of Capacitor Load.
The first process should accord two 3/1 rules,but how can i tweaking the MOS-FET in order to get better performance?


Thank U all!

 

[pixel]

cmos buffer sizing rule of thumb

Yes it is true. See last two pages of this chapter.

 

[marlboro_x]

buffer logic cmos

Thx very much.It really helps .I'll look it over...

 

[nittinsharma80]

super buffers in vlsi

Depending on the rise/fall and load drive specifications the inv for the buffer need to be sized.
also the super buffers require the sizing.
you can go through any good vlsi related book by Niel Weste or Pucknell or Rabey or Kang
they all are good and describe the sizing concepts