When I use chipscope 6.1i Analyzer to view the logic wave, I found that all of its port name are displayed as "DataPortxxx" or "TrigPort XXX" but not the PortName that displayed in CORE INSERTER when making connect?
Is there any method to use/import the portname that displayed in CORE INSERTER? I think it's very stupid to rename it one by one manually when Analyzing.
Please help me ,
thank you very much